1. Field of the Invention
The invention relates in general to leadless flip-chip packaging technology, and more particularly to a leadframe of leadless flip-chip package and a method for manufacturing the same.
2. Description of the Related Art
The conventional leadless flip-chip package uses a leadless leadframe to replace a flip-chip package substrate. A chip is flip-chip bonded onto the inner leads of the leadless leadframe to reduce packaging cost. The leadless leadframe for flip-chip bonding has to define a bump bonding region on the upper surface of the inner leads, otherwise the bump disposed on the chip will be spread to be outside the bump bonding region. According to the technology disclosed in Taiwanese Patent Publication No. 567598 “Semi-Conductor Chip Flip-Chip Package”, a plurality of recessions are formed on the upper surface of the inner leads to define the bump bonding region. According to the technology disclosed in Taiwanese Patent Publication No. 463342 “Quad Flat Package”, a solder mask layer is printed on the upper surface of the inner leads. The solder mask layer has a plurality of openings for defining a bump bonding region to facilitate the connection of the bumps on chip and control the bump collapse. The inner leads are different from the redistribution circuit of the conventional flip-chip package substrate, and can not be fixed onto the dielectric layer of the package substrate. Therefore, the length and the diameter of the inner leads fail to meet the requirement as to achieve the function of electrical redistributed connection and high density wiring. The dielectric layer can be a glass fabric with pre-impregnated resin for instance. Moreover, there are clearances existing between the inner leads, therefore impeding the formation of a quality printing carrying surface and the printing of the solder mask layer. The lower surface of the inner leads and the printing compound are easily contaminated by the solder mask layer. When the inner leads of the leadless leadframe are unable to achieve a redistribution design, the position of the chip bump needs to be reallocated. Conventionally, a redistribution circuit layer is made on the active surface of the chip. A leadless leadframe unable to achieve a redistribution design in response to the situation when the position of the chip bump varies from one chip to another (for example, the position of the bump may be arranged in grid arrays, a peripheral arrangement or a central arrangement) or when the outer terminal of the inner leads of leadless leadframe are of various specifications. The leadless leadframe are thus limited to a simple design of the inner leads of the leadframe, and can only seal the chips whose bumps are disposed on fixed positions. Therefore, the leadless leadframe can only replace a few number of flip-chip package substrates with simple circuit design, and are unable to widely replace the flip-chip package substrate in a lower cost.
A method for packaging a flip-chip bonded chip scale package is disclosed in Taiwanese Patent Publication No. 457662, “The Manufacturing Method and Structure of Chip Scale Package”. A leadless leadframe is formed during the packaging process . . . . The manufacturing process of forming the leadless leadframe can not precede the manufacturing process of packaging. But rather, the manufacturing process of packaging includes the step of manufacturing the leadless leadframe. A plurality of inner leads are formed by partly etching the top layer of a leadframe, which is a metal plate for instance, and the inner leads are carried by the under layer of the leadframe, so that the inner leads have a first end and a second end according to redistribution design. A semi-conductor chip is flip-chip bonded onto the inner leads, the chip bumps are connected to the first end of the inner leads. After an underfilling material is formed, the under layer of the leadframe is removed through etching. In the step of etching the under layer of the leadless leadframe, the chips are also etched at the same time, causing difficulties in operation and increasing failure rate in manufacturing process. Besides, in the step of etching to remove the under layer of the leadframe, in the absence of appropriate etching-stop point, the inner leads may be short-circuited if the inner leads are over-etched. After the step of etching and removing the under layer of the leadframe, the inner leads of the leadframe has an exposed lower surface. The exposed circuit needs extra protections; otherwise a short circuit would occur to naked circuits, making the manufacturing process difficult to control.